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 Features |
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 Code rate : 1/2, 1/3, 1/4 (constraint length K=9) |
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Encoder Generator Polynomial: |
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| Rate |
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K |
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G0 |
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G1 |
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G2 |
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G3 |
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| 1 / 2 |
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9 |
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753(8) |
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561(8) |
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| 1 / 3 |
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9 |
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557(8) |
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663(8) |
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711(8) |
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| 1 / 4 |
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9 |
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765(8) |
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671(8) |
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513(8) |
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473(8) |
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Datarate : up to 1Mbps |
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Decoding Mode : continuous or Frame |
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BER : 10-3 for voice, 10-5 for data |
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4-bit soft-decision |
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Applicable to 3GPP TrCH CODEC |
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| Logic Block Diagram |
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| Viterbi Decoder Core consists of Branch Metric Block, ACS(Add-Compare-Select) Block, ACS/TB (Trace-Back) memory, and control logic blocks. |
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